1. Field of the Invention
The present invention relates to a testing apparatus, a testing method, and a program that test a circuit subjected to inspection using test vector data in which an input signal to be inputted to the circuit subjected to inspection is described.
2. Description of the Related Art
In recent years, systems using electronic circuits are advanced with higher functions and more complexity. Consequently, hardware mounted in such a system has a larger circuit scale and increased complexity. In system design, verification of hardware and software is very important to ensure that a system behaves as specified.
In hardware design, verification of the functions occupies most of the design period. As the scale and complexity of the circuits increase, the number of person-hours for such verification of the functions is also increasing. With such a background, measures to shorten the verification of the functions are considered. Exemplary methods of shortening the verification period include a method of shortening the verification period by speedup of hardware simulations and a method of generating test vector data at random.
The techniques of test vector creation and verification related to test vectors are disclosed in Japanese Unexamined Patent Application Publication Nos. 2001-167141, 2006-58172, and 2007-47109.
Japanese Unexamined Patent Application Publication No. 2001-167141 discloses a fault simulator. This fault simulator executes a fault simulation of an integrated circuit having different component portions activated in correspondence with the operation mode, and classifies the test vectors based on circuit design data. The simulator then carries out a fault simulation of an integrated circuit per operation mode using the classified test vectors.
Japanese Unexamined Patent Application Publication No. 2006-58172 discloses a test pattern generation program. This test pattern generation program generates terminal information of a circuit based on a netlist, selects an activation test sequence that activates a terminal of the generated terminal information, and generates a test sequence using this activation test sequence.
In Japanese Unexamined Patent Application Publication No. 2007-47109, information included in test data, such as signal information, is classified into each type to create intermediate data and fail information is added to the intermediate data to create test data for fault analysis.
In such a manner, in Japanese Unexamined Patent Application Publication Nos. 2001-167141, 2006-58172, and 2007-47109, test vectors are created using circuit information, fault information, and the like or suitable test vectors are selected using circuit information, fault information, and the like.